Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility. Thoroughly comprehend both internal and external
Responsibilities: Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench,